10. CACHE Instructions
1. The processor reads the STag, PIdx, and State bits from both ways of the secondary tag array.
2. If the PA of the CACHE instruction matches the STag, and the State does not equal 00 (Invalid), a hit has occurred. If there is a hit, the STag is used to interrogate the primary caches. If there is not a hit, the instruction ends.
3. The processor reads each subset block from the primary instruction cache. If there is a match then invalidate the block by writing the IState bit to 0 (Invalid) and the IState parity bit to 0.
4. Read each subset block from the primary data cache. If there is a match then write the DState bits = 00 (Invalid), the StateMod bits = 001 (Normal), the SCWay bit = 0, and the DState parity bit = 0. If the original State of any subset block is StateMod = 0102 (Inconsistent), also write it back to the secondary cache using the DTag and the secondary way bit from the primary data tag array.
5. Write the State of the secondary cache block = 00 (Invalid). Since the secondary cache is designed so all tag bits must be written at once, the STag, PIdx, and ECC bits are also written. The STag is written with whatever the PA and VA[13:12] of the original CACHE instruction were. The Tag ECC is generated.
6. If the secondary block's original State bits were 112 (Dirty) then the block is written back to the system interface unit. If the block's State was Shared or CleanExclusive the system interface unit is simply notified that the block has been deleted with a "Tag Invalidation" request.
7. The MRU bit is set to point away from the block invalidated.
Hit WriteBack Invalidate (S) set the CH bit if it hits in the secondary cache. Once the CH bit is set it stays set until cleared by a MTC0 Instruction.
Hit CacheOps can cause cache error exceptions if they check ECC or parity bits.
